Analog comparators are fundamental building blocks of analog-to-digital converters (ADC's). Analog comparators often consist of two circuit blocks: a differential amplifier that amplifies the difference between a reference voltage and an analog input voltage, and a sense amplifier/regenerative latch (sense amp/latch). The sense amp/latch senses the amplified difference between the reference voltage and the analog input voltage and converts that difference into a digital 1 or a 0, based on whether the amplified voltage difference is positive or negative. FIG. 1A illustrates an example of a prior art comparator 100. Comparator 100 includes differential amplifier 102 and sense amp/latch 104. An input voltage V.sub.in and a reference voltage V.sub.ref are compared by comparator 100, and complementary outputs Q and Q are produced to indicate which input (V.sub.in or V.sub.ref) is higher.
A commonly used topology for a sense amp/latch 104 is shown in FIG. 1B. In FIG. 1B, transistors M.sub.IP and M.sub.IN comprise an input differential pair that accepts the positive (V.sub.P) and negative (V.sub.N) voltage outputs, respectively, from the amplifier 102 shown in FIG. 1A. Transistors M1 through M4 comprise a cross-coupled inverter pair that creates regenerative feedback in a well-known manner when device MS is opened and device MP is closed. The circuit of FIG. 1B accepts a differential input and produces a differential output. Optimally M.sub.IP, M3 and M1 should be matched in terms of their physical and electrical characteristics to their counterparts on the other half of the circuit (M.sub.IN, M4 and M2).
The conventional sense amp/latch 104 has two phases of operation: a combined reset/sense phase (a negative feedback mode) and a latching phase (a positive feedback mode). A representative scheme for driving a comparator that uses the sense amp/regenerative latch of FIG. 1B is shown in FIG. 2. Throughout this application and the accompanying drawing figures, the terms Q and Q, QR and QR, LATCH and LATCH, SENSE and SENSE, and the like are digital complements of each other, e.g., when LATCH is a digital 1, LATCH is a digital 0 (and vice versa).
Referring to FIGS. 1B and 2, during the combined reset/sense phase LATCH is high, device MS is closed, and device MP is opened; as a result, transistors M3 and M4 are electrically isolated from the power supply (V.sub.DD) and device MS brings nodes N1 and N2 substantially close to their common-mode voltage level (which is equal to the average gate-source voltages of M1 and M2) from their previous voltages (e.g., previous logic states) quickly. The combination of MS, M1 and M2 forms a differential load to the differential pair M.sub.IP and M.sub.IN, and the sense amp/latch 104 behaves like a differential amplifier in this mode. Thus, given enough time, nodes N2 and N1 develop a voltage between them of A* (V.sub.P -V.sub.N) where A is the gain of sense amp/latch 104 when it is behaving like a differential amplifier.
FIG. 3 shows an equivalent circuit to the circuit of FIG. 1B when it is operating in the latching phase. During the latching phase, LATCH is low, device MP is closed, and device MS is opened. As a consequence, the sources of devices M3 and M4 are electrically connected to the power supply (V.sub.DD) via device MP and the combination of transistors M1 through M4 operate as two back-to-back connected inverters and enable positive regenerative feedback (see FIG. 1B). The positive feedback causes the voltages on nodes N1 and N2 to change rapidly in opposite directions until the voltage on node N1 gets close to the supply rail (V.sub.DD) and the voltage on node N2 gets close to the ground rail, or vice versa, depending on the initial voltages on node N1 and node N2.
In the circuit of FIG. 1B, the single device MS affects both the reset and sensing operation of the combined reset/sense phase, and the optimization of device MS is important for a fast reset and latch operation. However, the sizing of device MS is determined by two conflicting requirements: the conductance of device MS needs to be large enough to reset the circuit quickly, so that previous latched decisions will have no influence on the current decision (no memory), yet small enough such that large voltage gain from the input differential signal (V.sub.P -V.sub.N) to the differential signal of nodes N2 and N1 (V.sub.N2 -V.sub.N1) occurs. Larger gain during the sensing operation provides a larger output to the latch; this results in faster latching and a smaller required input voltage to overcome the latch output offset. This is accomplished by selecting a size and control terminal voltage for device MS such that the conductance imposed by MS barely overcomes the negative conductance imposed by devices M1 and M2, so that the small signal conductance (inverse of the load resistance) formed substantially by the combination of M1, M2, and MS is small and positive. The two conflicting requirements (fast reset and large gain) limit the speed with which reset and latching can be performed for the circuit shown in FIG. 1B.